High beta output stage for high speed operational amplifier

ABSTRACT

The present invention provides an high beta, high speed operational amplifier output stage ( 100 ). The advantages of the operational amplifier output stage over conventional methods disclosed is up to β 2  rather than a single beta. The present invention achieves this using an pre-driver sub-stage ( 122 ) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage ( 123 ). The output of the disclosed operational amplifier output stage takes the form: 
     δ I   o   ≈β   n *β p   *δI   in . 
     When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention generally relates to electronic systems and inparticular to operational amplifier output stages.

BACKGROUND OF THE INVENTION

[0002] Operational amplifiers are used in many electronic circuits tocondition, manipulate and amplify signals. The operating characteristicsof a particular operational amplifier are dependent upon its circuittopology. Generally, the operational amplifier consists of a number ofstages, each containing internal sub-stages.

[0003] Two important operating characteristics of an operationalamplifier are its amplification characteristics and its speed. High beta(β) and high speed are desirable in operational amplifiers that have avariety of application, including DSL Drivers. Beta (β) refers to theratio of DC collector current to DC base current in a bipolar junctiontransistor or current gain from base to collector. β is very importantparameter that varies with collector current temperature.

SUMMARY OF THE INVENTION

[0004] The present invention achieves technical advantages as a high β,high speed operational amplifier output stage using a localized feedbacksystem in which current gains are close to β_(n)*β_(p), where β_(n)refers to the beta of either the pre-driver npn transistor, outputdriver npn transistor or an average of both, depending on the currentsignal and β_(p) refers to the beta of either the pre-driver pnptransistor, output pnp transistor or an average of both. Where signalcurrent is large and positive, load conduction is through the output npntransistor and pre-driver pnp transistor. Where signal current is largeand negative, load conduction is through the pre-driver npn transistorand output pnp transistor. Where the signal is small, load conductionvaries in tandem through the output npn transistors and pre-diver pnptransistor and the output pnp transistor and pre-driver npn transistor.

[0005] The output stage can be seen to comprise a pre-driver sub-stageand final sub-stage. The pre-driver sub-stage is further comprised of afirst and a second pre-driver sub-stage circuit. In addition, the finalsub-stage is further comprised of a first and a second final sub-stagecircuit. The input to the present invention comprises a transconductance(“g_(m)”) cell which, when a voltage is applied thereto, an errorvoltage appears across the input gm cell and an error current isproduced at the output of the input g_(m) cell. The error current(δI_(in)) flows into the emitters of two pre-driver sub-stagetransistors and flows out of their collectors into the bases of twoother pre-driver transistors. Through this translinear loop, no netsignal is lost. The gained up error currents then flow into the finalsub-stage translinear loop, specifically, into the bases of two finalsub-stage transistors. Effectively, in the small signal context, thefirst pre-driver sub-stage circuit amplifies a positive portion of thecurrent signal for output to the first final sub-stage circuit while thesecond pre-driver sub-stage circuit amplifies a negative portion of thecurrent signal for output to the second final sub-stage circuit. Thefirst and second final sub-stages further amplify the positive portionand negative portion, respectively, of the current signal.

[0006] The first and second final sub-stage circuits are interconnectedat an output terminal of the operational amplifier output stage suchthat the amplified positive portion of the signal and amplified negativeportion of the signal are joined substantially in phase, in the formδI_(o)≈B_(n)*B_(p)*δI_(in). By feeding back a portion of the outputsignal using a variety of feedback principles, speed characteristics canbe further improved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention,reference is made to the detailed description taken in conjunction withthe following drawings:

[0008]FIG. 1 is a circuit diagram of a first conventional operationalamplifier output stage;

[0009]FIG. 2 is a circuit diagram of a second conventional operationalamplifier output stage;

[0010]FIG. 3 is a graph illustrating the linearity characteristics ofthe first conventional operational amplifier. This figure shows thefirst derivative (δV_(o)/δV_(i)) of the amplifier's DC transfercharacteristic;

[0011]FIG. 4 is a graph illustrating the linearity characteristics ofthe second conventional operational amplifier. This figure shows thefirst derivative (δV_(o)/δV_(i)) of the amplifier's DC transfercharacteristic;

[0012]FIG. 5 shows the single ended and differential linearitycharacteristics of the first conventional operational amplifier outputstage using a discrete multi-tone (“DMT”) signal with missing tones;

[0013]FIG. 6 is a graph illustrating the typical linearitycharacteristics of the first conventional operational amplifier outputstage in harmonic distortion form;

[0014]FIG. 7 is a circuit diagram of a first embodiment of the presentinvention with a g_(m) cell input;

[0015]FIG. 8 is a circuit diagram of a second embodiment of the presentinvention with a g_(m) cell input;

[0016]FIG. 9 is a graph illustrating the linearity characteristics ofthe first embodiment of the present invention. This figure shows thefirst derivative (δV_(o)/δV_(i)) of the amplifier's DC transfercharacteristic;

[0017]FIG. 10 is a graph illustrating the linearity characteristics ofthe first embodiment of the present invention using a DMT signal withmissing tones;

[0018]FIG. 11 is a graph illustrating the linearity characteristics ofthe first embodiment of the present invention in harmonic distortionform;

[0019]FIG. 12 illustrates the translinear loop formed by the first,second, third and fourth transistors;

[0020]FIG. 13 illustrates the translinear loop formed by the fifth,sixth, seventh and eight transistors;

[0021]FIG. 14 is a circuit diagram of the final sub-stage of the firstembodiment of the present invention using type I biasing of the outputtransistors in a no-load configuration;

[0022]FIG. 15 is a circuit diagram of the final sub-stage of the firstembodiment of the present invention using type I biasing of the outputtransistors with a load;

[0023]FIG. 16 is a graph illustrating the current gain of the finalsub-stage of the first embodiment of the present invention;

[0024]FIG. 17 is a circuit diagram of the final sub-stage of the secondembodiment of the present invention using type II biasing of the outputtransistors in a no load configuration;

[0025]FIG. 18 is a circuit diagram of the final sub-stage of the secondembodiment of the present invention using type II biasing of the outputtransistors with a signal applied to such final sub-stage's input;

[0026]FIG. 19 is a graph illustrating the DC current transfercharacteristic of the final sub-stage of FIG. 18;

[0027]FIG. 20 is a graph illustrating the DC current transfercharacteristic of the final sub-stage of FIG. 15;

[0028]FIG. 21 is a graph illustrating the linearity characteristic ofthe final sub-stage of FIG. 15 and FIG. 18. This figure shows the firstderivative (δI_(o)/δI_(i)) of the amplifiers' DC current transfercharacteristics;

[0029]FIG. 22 is a circuit diagram of a conventional operationalamplifier illustrating bias setup for the output transistors;

[0030]FIG. 23 is a graph illustrating the DC current transfercharacteristics of circuit depicted in FIG. 22;

[0031]FIG. 24 is a circuit diagram of the first embodiment of thepresent invention with current feedback circuitry;

[0032]FIG. 25 is a circuit diagram of the first embodiment of thepresent invention with voltage feedback circuitry;

[0033]FIG. 26 is a circuit diagram of the second embodiment of thepresent invention with current feedback;

[0034]FIG. 27 is a circuit diagram of the second embodiment of thepresent invention with voltage feedback;

[0035]FIG. 28 is a graph comparing the linearity characteristics betweenthe two conventional operational amplifiers and the first and secondembodiments of the present invention. The figure shows the firstderivative of the amplifiers' gain.

[0036]FIG. 29 is a circuit diagram of the first embodiment of thepresent invention with a compound darlington output stage using type Ibiasing;

[0037]FIG. 30 is a circuit diagram of the first embodiment of thepresent invention with a compound darlington output stage using type Ibiasing and a differential pair input g_(m) cell;

[0038]FIG. 31 is a circuit diagram illustrating a current feedbackstability loop;

[0039]FIG. 32 is a circuit diagram implementing conventional Millercompensation using a current feedback with the embodiments of thepresent invention;

[0040]FIG. 33 is a circuit diagram illustrating a voltage feedbackstability loop;

[0041]FIG. 34 is a circuit diagram illustrating implementation ofconventional Miller compensation using voltage feedback to achieveright-half-plane zero is (“RHPZ”) cancellation with the embodiments ofthe present invention; and

[0042]FIG. 35 is a circuit diagram illustrating a method for achievinglow frequency precision in either of the first or second embodiments ofthe present invention.

DESCRIPTION OF CONVENTIONAL AMPLIFIER OUTPUT STAGES

[0043]FIG. 1 is a circuit diagram of a first conventional operationalamplifier output stage. FIG. 2 is a circuit diagram of a secondconventional operational amplifier output stage. FIG. 3 illustrates thelinearity characteristics of such first conventional operationalamplifier by showing the first derivative of the DC transfercharacteristic. FIG. 4 illustrates the linearity of such secondconventional operational amplifier by showing the first derivative ofthe DC transfer characteristic. FIG. 5 illustrates the single ended anddifferential linearity of such first conventional operational amplifierwith a discrete multi tone (“DMT”) signal with missing tones. DMT signalis a broadband signal containing many sinusoids spaced at equalintervals. The missing tone performance looks for intermodulationproducts from the broadband DMT signal in at a frequency where there isno sinewave present in the DMT signal. DMT is a rigorous test of anamplifier's linearity. FIG. 6 illustrates the typical linearity of suchfirst and second conventional operational amplifiers in harmonicdistortion form.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0044] Two embodiments of the present invention are shown in FIGS. 7 and8. As compared to the conventional operational amplifier output stagesas disclosed in FIGS. 1 and 2, the disclosed embodiments of anoperational amplifier output stage as shown in FIGS. 7 and 8, provide ahigh β output (up to β²) and high speed with significantly reducedcrossover distortion. Because of its high speed, the disclosed inventionhas the advantage of extended bandwidth. The disclosed operationalamplifier output stage comprises a pre-driver sub-stage utilizingtranslinear current loops and a final sub-stage. The final sub-stage ofthe operational amplifier output stage disclosed herein comprises acomplementary set of compound darlington transistors enclosed in alocalized feedback system.

[0045] As used herein, translinearity refers to the characteristics ofnon-linear circuits whose operation is based on the exponentialcurrent-voltage relationship of the bipolar junction transistor; βrefers to the ratio of DC collector current to DC base current in abipolar junction transistor or current gain from base to collector; αrepresents the fraction of signal current going into one half of thepre-driver sub-stage, λ refers to the fraction of signal current goinginto the other half of the pre-driver sub-stage, and A refers to theemitter area of the BJT in consideration.

[0046]FIG. 7 is a circuit diagram of the first embodiment of anoperational amplifier output stage having reduced supply current andhigh linearity constructed according to the teachings of the presentinvention. The circuit 100 includes an input g_(m) cell 121, pre-driversub-stage comprised of eight pre-driver sub-stage transistors 101, 102,103, 104, 105, 106, 107 and 108, a final sub-stage comprising four finalsub-stage transistors 109, 110, 111 and 112, and four current sources131, 132, 133 and 134. The input g_(m) cell 121 is configured to acceptan input voltage signal, produce an error voltage across its input, andproduce an output error current (δI_(in)).

[0047] As shown therein, a first voltage supply rail 41 is coupled to afirst node 51, a second voltage supply rail 42 is coupled to a fifthnode 55.

[0048] The first pre-driver sub-stage circuit consists of fourtransistors 101, 102, 103 and 104. In the first pre-driver sub-stagecircuit, the emitter of the first transistor 101 is coupled to the firstvoltage supply rail 41 at the first node 51, and the base of the firsttransistor 101 is coupled to a second node 52. The emitter of the secondtransistor 102 is also coupled to the second node 52; and its base iscoupled to a third node 53. The base and collector of the thirdtransistor 103 are also coupled to the third node 53. The collector andbase of the fourth transistor 104 are each coupled to a fourth node 54.The emitter of the fourth transistor 104 is coupled to the voltagesupply rail 41 at the first node 51.

[0049] The second pre-driver sub-stage circuit comprises fourtransistors 105, 106, 107 and 108. The second voltage supply rail 42 iscoupled to the fifth node 55. The emitter of the fifth transistor 105 iscoupled to the second voltage supply rail 42 at the fifth node 55 andits base is coupled to a the sixth node 56. The emitter of the sixthtransistor 106 is coupled to the sixth node 56 and its base is coupledto a seventh node 57. The collector of the sixth transistor 106 iscoupled to the second node 52. The base and collector of the seventhtransistor 107 are coupled to a seventh node 57 and its emitter iscoupled to an eighth node 58. The collector and base of the eighthtransistor 108 are coupled to the eighth node 58, and the emitter of theeighth transistor 108 is coupled to the second voltage supply rail 42 atthe fifth node 55.

[0050] The collector of the second transistor 102 and the emitter of thesixth transistor 106 are coupled to a common sixth node 56. The emitterof the second transistor 102 and the emitter of the sixth transistor 106are coupled to a common second node 52. The cross connectionadvantageously results in no error current being lost in the translinearloops.

[0051] A first current source 131 is coupled to the first voltage supplyrail 41 at the first node 51 and at the second node 52. A second currentsource 132 is coupled to the first voltage supply rail 41 at the firstnode 51 and at the seventh node 57. A third current source 133 iscoupled to the second voltage supply rail 42 at the fifth node 55 and atthe third node 53. A fourth current source 134 is coupled to the voltagesupply rail 42 at the fifth node 55 and at the sixth node 56.

[0052] The final sub-stage 123 comprises a complementary pair ofdarlington transistors. The first set of darlington transistors iscomprised of the ninth and tenth transistors 109 and 110. The emitter ofthe ninth transistor 109 is coupled to the collector of the firsttransistor 101 at a ninth node 59. The base and collector of the ninthtransistor 109 are coupled at a tenth node 60. The base of the tenthtransistor 110 is coupled to the ninth node 59, and the collector of thetenth transistor 110 is coupled to the first voltage supply rail 41 atthe first node 51.

[0053] The second set of darlington transistors is comprised of theeleventh and twelfth transistors 111 and 112. The emitter of theeleventh transistor 111 is coupled to the collector of the fifthtransistor 105 at an eleventh node 61. The base and collector of theeleventh transistor 111 are coupled to the base and collector of theninth transistor 109 at the tenth node 60. The base of the twelfthtransistor 112 is coupled to the eleventh node 61, and the collector ofthe twelfth transistor 112 is coupled to the second voltage supply rail42 at the fifth node 55. The twelfth node 62 couples the emitter of thetenth transistor 110 to the emitter of the twelfth transistor 112. Anoutput terminal 91 is coupled to the twelfth node 62. The twelfth node62 also interconnects the output terminal 91 to the g_(m) cell input121. The configuration of the ninth transistor 109 and eleventhtransistor 111 of the first embodiment of the present invention is alsoreferred to as type I biasing.

[0054] A second embodiment of the present invention is disclosed in FIG.8. The second embodiment is also referred to as type II biasing of theoutput transistors. In this second embodiment, the collectors of theninth transistor 109 and the eleventh transistor 111 are not coupled atthe tenth node 60. The collector of the ninth transistor 109 is coupledto the second voltage supply rail V_(ee) 42 at the fifth node 55 and thecollector of the eleventh transistor 111 is coupled to the first voltagesupply rail V_(cc) 41 at the first node 51. In this case the currentgain from the collectors of 101 or 105 to the output node 91 is theaverage of β_(n) and β_(p). This arrangement minimizes crossoverdistortion in the output signal. As used herein, β_(n) refers to thebeta of transistor 110 and β_(p) refers to the beta of transistor 101,where α=1 and λ=1; or β_(n) refers to the beta of transistor 105 andβ_(p) refers to the beta of transistor 112, where α=0 and λ=0, or, inthe small signal context, where α=0.5 and λ=0.5, β_(n) refers to theaverage of the beta of transistor 110 and transistor 105 and β_(p)refers to the beta of the average of transistor 101 and transistor 112,the relative contribution of each such pnp transistor and npn transistorto B_(n) and B_(p) varying proportionally with the variation in α and λ.

[0055]FIGS. 9, 10 and 11 illustrate different performance aspects of thepresent invention. Specifically, FIG. 9 shows the linearitycharacteristics of the first embodiment of the present invention,specifically the first derivative (δV_(o)/δV_(i)) of the amplifier's DCtransfer characteristic. FIG. 10 shows the linearity characteristics ofthe first embodiment of the present invention using a DMT signal withmissing tones. FIG. 11 shows the linearity characteristics of the firstembodiment of the present invention in harmonic distortion form.

[0056] As shown in FIG. 12, in the first embodiment of the presentinvention a translinear loop is formed by the third transistor 103,fourth transistor 104, second transistor 102 and first transistor 101.In operation, two sets of current flow into this first translinear loopwhich sets up a quiescent current through a branch 170 connected at thecollector of the first transistor 101. In addition, as shown in FIG. 13,a translinear loop is formed by the seventh transistor 107, the eighthtransistor 108, the sixth transistor 106 and the fifth transistor 105.Two sets of current flow in this second translinear loop which sets up aquiescent current through a branch 171 connected at a collector of thefifth transistor 105. These two quiescent currents establish the biascurrents for the respective tenth transistor 110 and for the twelfthtransistor 112 by means of translinear principles in the loop formed bythe ninth transistor 109, eleventh transistor 111, tenth transistor 110and twelfth transistor 112.

[0057] When an input voltage is applied to the input g_(m) cell 121, anerror voltage appears across the output of the input g_(m) cell 121 andan error current is produced. Advantageously, the cross-connection ofthe collector of the second transistor 102 to the emitter of the sixthtransistor 106, and the collector of the sixth transistor 106 to theemitter of the second transistor 102 ensures that whatever proportion ofthe error current flowing into the emitters of the second transistor 102and sixth transistor 106 also flows back out through the collectors ofthe second transistor 102 and the sixth transistor 106 into the bases ofthe first transistor 101 and the fifth transistor 105. Advantageously,there is no net signal loss in the pre-driver sub-stage translinearloops.

[0058] The error currents into the bases of the first transistor 101 andthe fifth transistor 105, are thus gained up by the pre-driver sub-stagecontribution of β_(p) and β_(n). These error currents flow into thetranslinear loop formed by the ninth transistor 109, eleventh transistor111, tenth transistor 110 and twelfth transistor 112. These amplifiederror currents can only flow into the bases of the tenth transistor 110and twelfth transistor 112, where they are amplified by the finalsub-stage contribution of β_(n) and β_(p) respectively. Thus,irrespective of whether the error current flows through the top or thebottom route through the circuit it appears at the output terminal 91amplified by approximately β_(n) multiplied by β_(p), where it developsa correction voltage across the load resistor to move the output to apoint of minimum error of the feedback into the input g_(m) cell 121.

[0059] Output Transistor Biasing

[0060]FIG. 14 is a circuit diagram of the final sub-stage 123 of thefirst embodiment of the operational amplifier output stage in a no loadconfiguration. FIG. 14 illustrates type I biasing of the outputtransistors as follows: Current is flowing into the collector of thetenth transistor 110, referred to as I_(Q110C), and current is flowingout of the collector of the twelfth transistor 112, referred to asI_(Q112C). The emitter area of the ninth transistor 109 is referred toas A_(Q109) and the emitter area of the eleventh transistor 111 isreferred to as A_(Q111). The emitter area of the tenth transistor 110 isreferred to as A_(Q110) and the emitter area the twelfth transistor 112is referred to as A_(Q112). Two current sources I₁₃₅ and I₁₃₆ are shownthereon:$I_{135} = {{I + {\frac{\delta \quad I_{sig}}{2}\quad {and}\quad I_{136}}} = {I - \frac{\delta \quad I_{sig}}{2}}}$

[0061] Therefore,$\frac{I_{135}^{2}}{A_{Q109}*A_{Q111}} = \frac{I_{Q110C}*I_{Q112C}}{A_{Q112}*A_{Q110}}$

 for β_(n) and β_(p)>>1 and VA_(n) and VA_(p)>>1,

I_(Q110C)=I_(Q112C)=I_(C).

[0062]${Therefore},{{\frac{I_{135}^{2}}{A_{Q109}*A_{Q111}} = \frac{I_{C}^{2}}{A_{Q112}*A_{Q110}}};{{and}\quad {futher}}}$$I_{C} = {I_{135} \cdot \sqrt{\frac{A_{Q110}*A_{Q112}}{A_{Q109}*A_{Q111}}}}$

[0063]FIG. 15 is a circuit diagram of the final sub-stage 123 of thefirst embodiment of the present invention with a load 43. Type I biasingof the output transistors is thus described as follows: When a load 43is connected to the output terminal 91 and the following do not hold:

β_(n) and β_(p)>>1, or

VA_(n) and VA_(p)>>1, or

[0064] there is an imbalance between current I_(Q110C) and I_(Q112C).

[0065] Since current I_(Q110C) is not equal to I_(Q112C), an errorcurrent flows in the load 43 thus developing an offset voltage V_(error)across the load 43.

[0066] When the difference in current in the final sub-stage transistors110 and 112, are taken care of by a localized feedback system, thecharacteristics of the final sub-stage can be seen as follows: Thesignal current changes the bias currents by increasing the currentthrough the top circuit and decreasing the current through the bottomcircuit. In the limiting case for large current through the top circuitand miniscule current through the bottom circuit, and α is equal to one(1), the translinear loop cuts off the twelfth transistor 112 and all ofthe signal current flows into the base of the tenth transistor 110 whereit appears in the load 43 as follows:

β_(n)*(δI_(sig)).

[0067] Conversely, for large signal current through the bottom circuitand miniscule current at the top circuit, and where α is equal to 0, thetranslinear loop is again cut off and all of the signal current flowsinto the base of the twelfth transistor 112 where it appears in the load43 as follows:

β_(p)*(δI_(sig)).

[0068] For small signal currents, where α is close to half (0.5), thetranslinear loop is active, that is a quiescent current is flowingthrough both the tenth transistor 110 and the twelfth transistor 112,the signal current splits with α and (1−α) multiplied by δI_(sig)flowing into the base of the twelfth transistor 112. Thus the currentgain from input to output is as follows:

α*β_(n)+(1−α)*β_(p),

[0069] for all cases of α such that α is equal to or greater than zeroand equal to or less than 1.

[0070] As shown in the graph of FIG. 16, the gain will transition fromβ_(p) to β_(n) through the translinear region.

[0071]FIG. 17 is a circuit diagram of the final sub-stage of the secondembodiment of an operational amplifier in a no load configuration. FIG.17 illustrates type II biasing of the output transistors as follows:${\frac{\beta_{n}*\beta_{p}*i_{b}^{2}}{A_{Q109}*A_{Q111}} = \frac{I_{Q110C}*I_{Q112C}}{A_{Q112} - A_{Q110}}},{and}$$\frac{\beta_{n}*\beta_{p}*i_{b}^{2}}{A_{Q109}*A_{Q111}} = {\frac{\left( {{\beta_{n}^{*}I} - {\beta_{p}*\beta_{n}*i_{b}}} \right)\left( {{\beta \quad I} - {\beta_{n}*\beta_{p}*i_{b}}} \right)}{A_{Q112} - A_{Q110}}.}$

[0072] The current through branch 70 is: β_(p)*i_(b).

[0073] The current through branch 75 is: I−β_(p)*i_(b).

[0074] The current through branch 72 is: β_(n)*i_(b).

[0075] The current through branch 74 is: I−β_(n)*i_(b).

[0076] The current through branch 76 is: β_(n)*I−β_(p)*β_(n)*i_(b).

[0077] The current through branch 77 is: β_(p)*I−β_(n)*β_(p)*i_(b).

[0078] As can be seen, an offset current (β_(n)−β_(p))*I will develop anoffset voltage in a load, and would self correct in the localizedfeedback circuit.

[0079] Referring to FIG. 18, which illustrates type II biasing of theoutput transistors:

[0080] The current through branch 75 is: I+δI−β_(p) i_(b).

[0081] The current through branch 74 is: I+δI−β_(n) i_(b).

[0082] The current is through branch 76 is:(β_(n)*I)+(β_(n)*δI)−(β_(n)*β_(p)*i_(b)).

[0083] The current through branch 77 is:(β_(p)*I)−(β_(p)*δI)−(β_(n)*β_(p)*δI).

[0084] Thus, the output current through branch 78 is:i_(o)=I*(β_(n)−β_(p))+(β_(n)+β_(p))*δI.

[0085] This result theoretically indicates no crossover distortion inthe output, albeit with an offset.

[0086]FIGS. 19, 20 and 21 illustrate the-current drive relationships ofthe type I and type II biasing schemes.

[0087] Pre-Driver Biasing

[0088]FIG. 22 is a circuit diagram illustrating one technique of biascurrent generation for a rail to rail output stage in a conventionaloperational amplifier. The main disadvantage of this configuration isthat current gain from the input to the output is only a single β. Alsothis type of stage will have a large output impedance makingcompensation more difficult given variation in a load's impedance. Inthe first and second embodiments of the present invention, translinearprinciples are used to establish the bias currents in the pre-driverstage.

[0089] Referring back to FIGS. 7 and 8, if there is a slight mismatch inthe currents through the second transistor 102 and sixth transistor 106due to an Early voltage mismatch between these two devices, a cascode onthe second transistor 102 and the sixth transistor 106 will remedy thiseffect.

[0090] Also referring to FIGS. 7 and 8, assume that feedback introducesa correction term into the circuit to establish equality of collectorcurrents in the first transistor 101 and the fifth transistor 105, then:

I_(Q101C)=I_(Q105C)=I_(Qpre)

[0091] Thus, from translinear principles: $\begin{matrix}{{{1.\quad \frac{I_{132}^{2}}{A_{Q107}*A_{Q108}}} = {\frac{I_{Q106C}}{A_{Q106}}*\frac{I_{Qpre}}{A_{Qpre}}}};} & \quad \\{{{2.\quad \frac{I_{132}^{2}}{A_{Q103}*A_{Q104}}} = {\frac{I_{Q102C}}{A_{Q102}}*\frac{I_{Qpre}}{A_{Qpre}}}};} & \quad \\{{{{3.\quad I_{Q106C}} + I_{Q102C}} = I_{131}};} & \quad \\{{{{4.\quad \frac{I_{132}^{2}}{A_{Q107}*A_{Q108}}} = {{\frac{A_{Q101}}{I_{Q_{pre}C}}*A_{Q106}} = I_{Q106C}}};}\quad \text{(derived from equation 1);}} & \quad \\{{{{5.\quad \frac{I_{132}^{2}}{A_{Q103}*A_{Q104}}} = {{\frac{I_{Q105}}{A_{Q_{pre}C}}*A_{Q102}} = I_{Q102C}}};}\quad \text{(derived from equation 2);}} & \quad \\{{{{6.\quad \frac{I_{132}^{2}}{A_{Q107}*A_{Q108}}*\frac{I_{Q105}}{A_{Q_{pre}C}}*A_{Q106}} + {\frac{I_{132}^{2}}{A_{Q103}*A_{Q104}}*\quad \frac{A_{Q101}}{I_{Q_{pre}C}}*A_{Q102}}} = I_{131}};\text{(derived from equations 3, 4 and 5)}} & \quad\end{matrix}$

${Thus},{I_{Q_{pre}C} = {\frac{I_{132}^{2}}{I_{131}}{\left( {\frac{A_{Q105}*A_{Q106}}{A_{Q107}*A_{Q108}} + \frac{A_{Q101}*A_{Q102}}{A_{Q103}*A_{Q104}}} \right).}}}$

[0092] Referring to the operational amplifier output stage 100 shown inFIG. 7, the change in current in the first transistor 101 and the fifthtransistor 105 in response to a change in input current is computed asfollows: The input current change takes the form of an equal butopposite change in I_(X) and I_(Y) given that the difference currentbetween I_(X) and I_(Y) (i.e. δI) has to be divided between the bases ofthe first transistor 101 and the fifth transistor 105. Therefore,

I _(o) =I _(Y) −α*δI*β _(p) −I _(Y)−(1−α)δI−β _(n)

δI _(o) =−α*δI*β _(p)−(1−α)*δI*β _(n);

δI _(o) =−δI(α*β_(p)+(1−α)−β_(n)).

[0093] Where α is greater than zero and less than one, the value of αindicates the proportion of δI delivered into the bases of each of thepre-driver transistors, first transistor 101 and fifth transistor 105.

[0094] Where α is approximately zero, I_(X) has significantly increasedand I_(Y) has significantly decreased by equal and opposite quantities.The base-emitter voltage is large in the second transistor 102 and smallin the sixth transistor 106. The second transistor 102 cuts off and allof the difference current between I_(X) and I_(Y) (i.e. δI) flows intothe base of the fifth transistor 105. This gives a current gain in thecircuit of β_(n).

[0095] Where α is approximately equal to one, the opposite of where α isapproximately equal to zero occurs. Where I_(X) significantly decreases,I_(Y) significantly increases causing all difference current, δI, toflow into base of the first transistor 101, resulting in a current gainof β_(p).

[0096] Where α is greater than zero but less than one, the pre-driversub-stage 122 is in translinear mode. The difference current is split invarying proportion into the first transistor 101 and the fifthtransistor 105. Thus, δI_(o)/δI=α*β_(p)+(1−α)*β_(n).

[0097] Referring to FIG. 23, the DC response of the pre-driver sub-stage122 of the present invention is shown.

[0098] In connection with the coupling of the pre-driver sub-stage 122to the final sub-stage 123, the biasing scheme of the pre-drivers andthe biasing scheme of the final drivers of the present invention havethe advantageous property of not absorbing any signal current. All ofthe signal current is delivered directly into the bases of thetransistors, and none is lost in translinear loops.

[0099] The current gain from the input to the output has approximatelythe form:

δI _(o)≈β_(n)*β_(p) *∂I _(in).

[0100] Feedback Analysis

[0101] When feedback is locally applied by means of some localizedfeedback circuit, the errors are corrected within a very tight loopwhich will respond much more quickly than relying on the amplifieroverall feedback loop. This localized feedback provides the presentinvention with high speed capabilities.

[0102] Four (4) possibilities are presented: (i) current feedback,transitional β output (ii) current feedback, constant β output (iii)voltage feedback, transitional β output, and (iv) voltage feedback,constant β output.

[0103]FIG. 24 is a circuit diagram of a first embodiment of the presentinvention with a current feedback circuitry. FIG. 25 is a circuitdiagram of the first embodiment of the present invention with a voltagefeedback circuitry.

[0104] When the input g_(m) cell 121 takes the form of a complementarydifferential pair, the inherent RHPZ appearing when the pre-driversub-stage is Miller compensated vanishes as the feed forward termcontributing to the RHPZ is pulled back out by the differential pair.

[0105]FIG. 28 illustrates the output in a closed loop configuration with[greater than unity gain] driving a heavy load over a wide voltagerange. In all cases the worst ease non-linearity is approximatelyplus/minus 1 part in 1000. For the current feedback, constant β output,cross-over distortion is virtually eliminated.

[0106]FIG. 29 is a circuit diagram of the first embodiment of thepresent invention with a compound darlington output stage using type Ibiasing. A generalized evaluation of this circuit is as follows:

[0107] Referring to current through branches 150, 152, 154 156, 158,160, 172 and 174 in FIG. 29:

[0108] Current through branch 150 is I_(LTP); where I_(LTP) refers tothe current through current source 131.

[0109] Current through branch 152 is: −α·δI.

[0110] Current through branch 154 is:$\frac{I_{LTP}}{2} + {\delta \quad {{I\left( {\frac{1}{2} - \alpha} \right)}.}}$

[0111] Current through branch 156 is:$\frac{I_{LTP}}{2} - {\frac{\delta \quad I}{2}.}$

[0112] Current through branch 158 is:$\frac{I_{LTP}}{2} + {\frac{\delta \quad I}{2}.}$

[0113] Current through branch 160 is: I_(bias p)−β_(Q101)·α·δI.

[0114] Current through branch 162 is approximately$I_{{bias}\quad p} - \frac{I_{LTP}}{2} - {\delta \quad {I \cdot \beta_{Q101} \cdot {\alpha.}}}$

[0115] Current through 172 is: −λ·δI(β_(Q101)·α+β_(Q105)(1−α)).

[0116] Current through 174 is: −λ·δI·(β_(Q101)·α+β_(Q105)(1−α))+I_(bias out).

[0117] Referring to current through branches 151, 153, 155, 157, 159,161, 163, 173 and 175:

[0118] Current through branch 151 is I_(LTP); where I_(LTP) refers tothe current through current source 134 which is the same as the currentthrough current source 131.

[0119] Current through branch 153 is: (1−α) δI.

[0120] Current through branch 155 is:$\frac{I_{LTP}}{2} + {\delta \quad {{I\left( {\frac{1}{2} - \alpha} \right)}.}}$

[0121] Current through branch 157 is:$\frac{I_{LTP}}{2} + {\frac{\delta \quad I}{2}.}$

[0122] Current through branch 159 is:$\frac{I_{LTP}}{2} - {\frac{\delta \quad I}{2}.}$

[0123] Current through branch 161 is: I_(bias p)+β_(Q105)·(1−α)δI.

[0124] Current through branch 163 is:$I_{{bias}\quad p} - \frac{I_{LTP}}{2} + {{\beta_{Q105} \cdot \left( {1 - \alpha} \right)}\delta \quad {I.}}$

[0125] Current through branch 173 is: (1−λ)·δI(β_(Q101)·α+β_(Q105)(1−α).

[0126] Current through 175 is: (1−λ)−δI(β_(Q101)·α+β_(Q105)(1−α)+I_(bias out).

[0127] Therefore:

I _(out) =−λ·δI·β _(Q110)·(β_(Q101)·α+β_(Q105)(1−α))−(1−λ)·δI·β_(Q112)(β_(Q101)·α+β_(Q105)(1−α)).

[0128] In a first case where I_(out) is large and positive, and loadconduction is through transistor 110 and transistor 101, where α=1, λ=1,then:

I _(out) =−δI·β _(Q110)·β_(Q101)

[0129] In a second case where I_(out) is large and negative, and loadconduction is through transistor 112 and transistor 105, where α=0, λ=0,then:

I _(out) =−δI·β _(Q112)·β_(Q105)

[0130] In a third case where I_(out) is very small through thecross-over point, and load conduction is through transistor 110 andtransistor 112, where α≈0.5, λ≈0.5, then:$I_{out} = {{- \delta}\quad {I\left( \frac{\beta_{Q101} + \beta_{Q105}}{2} \right)}\left( \frac{\beta_{Q110} + \beta_{Q112}}{2} \right)}$

[0131] Thus, for β_(Q112)=β_(Q101)=β_(p)

[0132] and β_(Q110)=β_(Q105)=β_(n)$I_{out} = {{- \delta}\quad {I\left( \frac{\beta_{p} + \beta_{n}}{2} \right)}^{2}}$

[0133]FIG. 30 is a circuit diagram of the first embodiment of thepresent invention with a compound darlington output stage using type Ibiasing and a differential pair input g_(m) cell. A specific evaluationof this circuit is as follows:

[0134] Referring to the current through branches 140, 142, 152, 160, 172and 174 in FIG. 30:

[0135] The current through branch 140 is:

I ₁₃₁ +δI(½−α)

[0136] The current through branch 142 is: $- \frac{\delta \quad I}{2}$

[0137] The current through branches 152, 160, 172 and 174 are the sameas that in the equivalent numbered branches in FIG. 29.

[0138] Referring to the current through branches 141, 143, 153, 161,173, and 175 in FIG. 30:

[0139] The current through branch 141 is:

I ₁₃₄ +δI(½−α)

[0140] The current through branch 143 is: $\frac{\delta \quad I}{2}$

[0141] The current through branches 153, 161, 173 and 175 are the sameas that in the equivalent numbered branches in FIG. 29.

[0142] Therefore:

I _(out) =−λ·δI·β _(Q110)·(β_(Q101)·α+β_(Q105)(1−α))−(1−λ)·δI·β_(Q112)(β_(Q101)·α+β_(Q105)(1−α))

[0143] Referring to FIG. 30, and as noted in FIG. 29, in a first case,where I_(out) is large and positive, and load conduction is throughtransistor 110 and transistor 101, where α=1, λ=1, then:

I _(out) =−δI·β _(Q110)·β_(Q101)

[0144] In a second case where I_(out) is large and negative, and loadconduction is through transistor 112 and transistor 105, where α=0, λ=0,then:

I _(out) =−δI·β _(Q112)·β_(Q105)

[0145] In a third case, where case I_(out) is very small through thecross-over point, and load conduction is through transistor 110 andtransistor 112, where α≈0.5, λ≈0.5, then:$I_{out} = {{- \delta}\quad {I\left( \frac{\beta_{Q101} + \beta_{Q105}}{2} \right)}\left( \frac{\beta_{Q110} + \beta_{Q112}}{2} \right)}$

[0146] Thus, for β_(Q112)=β_(Q101)=β_(p)

[0147] and β_(Q110)=β_(Q105)=β_(n)$I_{out} = {{- \delta}\quad {I\left( \frac{\beta_{p} + \beta_{n}}{2} \right)}^{2}}$

[0148] where 0<α<1;

[0149] and 0<λ<1.

[0150] I_(biasp) and I_(biasout) are established using translinearprinciples.

[0151] Compensation

[0152]FIGS. 31, 32, 33 and 34 show the various types of compensationtechniques that can be used with the present invention. FIG. 31 is ahalf circuit showing the current feedback case with small signal AC. Thecircuit is a 2 voltage gain stage amplifier with voltage gain beingdeveloped at nodes 63 and 64. The circuit lends itself to classic Millercompensation as shown in FIG. 31.

[0153] Referring to FIG. 32, the resistor 81 eliminates the right halfplane through the compensation capacitor 85. At the quiescent condition,the value is the reciprocal of the transconductance of the firsttransistor 101.

[0154]FIG. 33 illustrates the voltage feedback case. Referring to thecircuit in FIG. 33, there are two (2) loops to be compensated, innerloop 2 and outer loop 1. As can be seen in FIG. 32, similar to thecurrent feedback implementation, the system is a 2 voltage gain stageamplifier with voltage gain at nodes 63 and 64. This circuit can also beMiller compensated. There is no concern with RHPZ because thedifferential transistor 113 draws the feed forward signal out.

[0155] Implementation

[0156] It is noted that the voltage feedback implementation can only beused for gain greater than 1. Further, the current feedbackimplementation can be used for arbitrary gain. All four implementationscan be used as a stand alone amplifier configuration.

[0157]FIG. 35 illustrates how gain from the present invention can bepreserved where additional lower frequency precision is required.

[0158] The advantages of the present invention over conventionaloperational amplifier output stages is significantly higher linearityfor the same supply current or linearity equal to the conventionaloperational amplifiers.

[0159] The current gain obtained in the error correction loop of each ofthe first and second conventional operational amplifiers is only asingle current gain whereas the current gain of the present invention isup to β². Further, the DC non-linearity of conventional amplifiers isapproximately 2 parts per 1000, a factor of 25 worse than the presentinvention. Reduced current draw is one of the advantages afforded by thedesign of each of the present invention.

[0160] The numerous innovative teachings of the present application aredescribed with particular reference to the disclosed embodiments.However, it should be understood that these embodiments provide only twoexamples of the many advantageous uses and innovative teachings herein.Various alterations, modifications and substitutions can be made to thedisclosed invention without departing in any way from the spirit andscope of the invention, as defined in the claims that follow. Forexample, although the embodiments have been presented herein withreference to particular transistor types, voltage and current polaritiesand methods of coupling, the present inventive structures andcharacteristics are not necessarily limited to particular transistortypes, polarities or methods of coupling, as used herein. It should beunderstood the embodiment used hereinabove can easily be implementedusing many diverse transistor types, polarities and methods of couplingso long as the combinations achieve an ultra linear, high speedoperational amplifier output stage with reduced current draw andextended bandwidth.

What is claimed is:
 1. An operational amplifier output stage,comprising: a pre-driver sub-stage and a final sub-stage, the pre-driversub-stage having a plurality of transistors being biased by a pluralityof current sources, the pre-driver sub-stage being adapted to accept acurrent signal (δI_(in)) from an input g_(m) cell; the pre-driver stagebeing further adapted to provide biasing to a plurality of transistorsin the final sub-stage; and the pre-driver sub-stage being coupled tothe final sub-stage so as to provide current gain from input to outputof δI_(o)≈β_(n)*β_(p)*δI_(in); and localized feedback circuitry enclosedin the output stage operable to correct signal errors more rapidly thanan overall amplifier feedback loop, thereby improving the speedcharacteristics of the operational output stage.
 2. The operationalamplifier output stage recited in claim 1, further comprising inherentRHPZ cancellation operable to extend bandwidth.
 3. The operationalamplifier output stage recited in claim 1, wherein the plurality oftransistors in the final sub-stage comprises 4 transistors arranged as acomplementary pair of differential transistors enclosed in a localizedfeedback system.
 4. The operational amplifier output stage recited inclaim 1 for use in an integrated circuit.
 5. The operational amplifieroutput stage recited in claim 1 for use in a DSL driver.
 6. Anoperational amplifier output stage, comprising: a pre-driver sub-stagehaving a plurality of transistors configured as translinear loops suchthat there is minimal net signal loss or signal attenuation in thepre-driver sub-stage; a final sub-stage coupled to, and biased bycurrents from, the pre-driver sub-stage, operable to provide up to β²;and a localized feedback circuitry and inherent RHPZ in the output stageoperable to improve speed characteristics and extend bandwidth.
 7. Anoperational amplifier output stage, comprising: a first voltage supplyrail V_(cc) connected to a first node; two connection terminals to aninput stage, a first terminal connected to a second node for receiving apositive portion of an input signal and a second terminal connected to asixth node for receiving a negative portion of an input signal; a firstpre-driver sub-stage circuit coupled at the second node, the firstpre-driver sub-stage circuit further comprising: a first transistorhaving its emitter coupled to the first voltage supply rail V_(cc) atthe first node, and its base coupled at the second node; a secondtransistor having its emitter coupled to the second node and its basecoupled to a third node; a third transistor having its base andcollector coupled to the third node; a fourth transistor having itscollector and base being coupled to a fourth node, and its emittercoupled to the first voltage supply rail V_(cc) at the first node; asecond voltage supply rail V_(ee) coupled to a fifth node; a secondpre-driver sub-stage circuit coupled to the sixth node, the secondpre-driver sub-stage circuit further comprising: a fifth transistorhaving its emitter coupled to the second voltage supply rail V_(ee) atthe fifth node, and its base coupled to the sixth node; a sixthtransistor having its emitter coupled to the sixth node, its basecoupled to a seventh node, and its collector coupled to the second node;a seventh transistor having its base and collector coupled to a seventhnode; and its emitter coupled to an eighth node; an eighth transistorhaving its collector and base being coupled to the eighth node, and itsemitter coupled to the second voltage supply rail V_(ee) at the fifthnode; a cross connection between the second transistor's collector andthe sixth transistor's emitter at the sixth node, and the secondtransistor's emitter and the sixth transistor's collector at the secondnode, the cross connection resulting in a proportion of any errorcurrent flowing into the second transistor's emitter and sixthtransistor's emitter to flow out through the second transistor'scollector and the sixth transistor's collector into the base of thefirst transistor and the base of the fifth transistor; a first currentsource coupled between the first voltage supply rail V_(cc) at the firstnode and the second node; a second current source coupled between thefirst voltage supply rail V_(cc) at the first node and the seventh node;a third current source coupled between the second voltage supply railV_(ee) at the fifth node and at the third node; a fourth current sourcecoupled between the second voltage supply rail V_(ee) at the fifth nodeand the sixth node; a final sub-stage, comprising: a first finalsub-stage circuit further conditioning the positive portion of thecurrent signal provided by the first pre-driver sub-stage circuit, thefirst final sub-stage circuit comprising: a ninth transistor having itsemitter coupled to the first transistor's collector at a ninth node, andits base and collector coupled to a tenth node; a tenth transistorhaving its base coupled to the ninth node, and its collector coupled tothe first voltage supply V_(cc) rail at the first node; a second finalsub-stage circuit further conditioning the negative portion of thecurrent signal, provided by the second pre-driver sub-stage circuit, thesecond final sub-stage circuit comprising: an eleventh transistor havingits emitter coupled to the fifth transistor's collector at an eleventhnode, its base and collector coupled to the ninth transistor's base andcollector at the tenth node; a twelfth transistor having its basecoupled to the eleventh node, and its collector coupled to the secondvoltage supply rail V_(ee) at the fifth node; a twelfth nodeinterconnecting the tenth transistor's emitter with the twelfthtransistor's emitter; and an output terminal coupled to the twelfthnode; and localized feedback circuitry enclosed within the operationalamplifier output stage.
 8. The operational amplifier output stagerecited in claim 7 wherein the first, second, third, fourth, ninth andtwelfth transistors are pnp transistors and the fifth, sixth, seventh,eight, tenth and eleventh transistors are npn transistors.
 9. Theoperational amplifier output stage recited in claim 7, including alocalized feedback circuitry enclosed within the operational amplifieroutput stage.
 10. The operational amplifier output stage recited inclaim 7, wherein the localized feedback circuitry utilizes currentfeedback principles operable to substantially eliminate cross-overdistortion.
 11. An operational amplifier output stage, comprising: afirst voltage supply rail V_(cc) connected to a first node; twoconnection terminals to an input stage, a first terminal connected to asecond node for receiving a positive portion of a current signal and asecond terminal connected to a sixth node for receiving a negativeportion of a current input signal; a first pre-driver sub-stage circuitcoupled at the second node, the first pre-driver sub-stage circuitfurther comprising: a first transistor having its emitter coupled to thefirst voltage supply rail V_(cc) at the first node, and its base coupledat the second node; a second transistor having its emitter coupled tothe second node and its base coupled to a third node; a third transistorhaving its base and collector coupled to the third node; a fourthtransistor having its collector and base being coupled to a fourth node,and its emitter coupled to the first voltage supply rail V_(cc) at thefirst node; a second voltage supply rail V_(ee) coupled to a fifth node;a second pre-driver sub-stage circuit coupled to the sixth node, thesecond pre-driver sub-stage circuit further comprising: a fifthtransistor having its emitter coupled to the second voltage supply railV_(ee) at the fifth node, and its base coupled to the sixth node; asixth transistor having its emitter coupled to the sixth node, its basecoupled to a seventh node, and its collector coupled to the second node;a seventh transistor having its base and collector coupled to a seventhnode; and its emitter coupled to an eighth node; an eighth transistorhaving its collector and base being coupled to the eighth node, and itsemitter coupled to the second voltage supply rail V_(ee) at the fifthnode; a cross connection between the second transistor's collector andthe sixth transistor's emitter at the sixth node, and the secondtransistor's emitter and the sixth transistor's collector at the secondnode, the cross connection resulting in a proportion of any errorcurrent flowing into the second transistor's emitter and sixthtransistor's emitter to flow out through the second transistor'scollector and the sixth transistor's collector into the base of thefirst transistor and the base of the fifth transistor; a first currentsource coupled between the first voltage supply rail V_(cc) at the firstnode and the second node; a second current source coupled between thefirst voltage supply rail V_(cc) at the first node and the seventh node;a third current source coupled between the second voltage supply railV_(ee) at the fifth node and at the third node; a fourth current sourcecoupled between the second voltage supply rail V_(ee) at the fifth nodeand the sixth node; a final sub-stage, comprising: a first finalsub-stage circuit further conditioning the positive portion of thecurrent signal provided by the first pre-driver sub-stage circuit, thefirst final sub-stage circuit comprising: a ninth transistor having itsemitter coupled to the first transistor's collector at a ninth node, andits base coupled to a tenth node and its collector coupled to the secondvoltage supply rail V_(ee) at the fifth node; a tenth transistor havingits base coupled to the ninth node, and its collector coupled to thefirst voltage supply V_(cc) rail at the first node; a second finalsub-stage circuit further conditioning the negative portion of thecurrent signal, provided by the second pre-driver sub-stage circuit, thesecond final sub-stage circuit comprising: an eleventh transistor havingits emitter coupled to the fifth transistor's collector at an eleventhnode, its base coupled to the ninth transistor's base and collector atthe tenth node and its collector coupled to the first voltage supplyrail V_(cc) at the first node; a twelfth transistor having its basecoupled to the eleventh node, and its collector coupled to the secondvoltage supply rail V_(ee) at the fifth node; a twelfth nodeinterconnecting the tenth transistor's emitter with the twelfthtransistor's emitter; an output terminal coupled to the twelfth node;and localized feedback circuitry enclosed within the operationalamplifier output stage.
 12. The operational amplifier output stagerecited in claim 11, wherein the localized feedback circuitry utilizescurrent feedback principles.
 13. The operational amplifier output stagein claim 11, wherein the localized feedback circuitry utilizes voltagefeedback principles.
 14. The operational amplifier output stage recitedin claim 11, wherein the first, second, third, fourth, ninth and twelfthtransistors are pnp transistors, and the fifth, sixth, seventh, eighth,tenth and eleventh transistors are npn transistors.
 15. A method ofamplifying a signal, comprising the steps of: biasing a plurality oftransistors in a pre-driver sub-stage; biasing a plurality oftransistors in a final sub-stage; routing the positive cycle of thesignal through a first, biased pre-driver sub-stage circuit; routing thenegative cycle of the signal through a second, biased pre-driversub-stage circuit; amplifying the positive cycle of the signal in thefirst, biased pre-driver sub-stage circuit; amplifying the negativecycle of the signal in the second, biased pre-driver sub-stage circuit;routing the amplified positive cycle of the signal to a first, biasedfinal sub-stage circuit; routing the amplified negative cycle of thesignal to a second, biased final sub-stage circuit; further amplifyingthe positive cycle of the signal in a first, biased final sub-stagecircuit in tandem with the pre-driver sub-stage amplification action;further amplifying the negative cycle of the signal in a second, finalsub-stage circuit in tandem with the pre-driver sub-stage amplificationaction; employing a plurality of translinear loops in the pre-driversub-stage circuits and final sub-stage circuits so as to preserve theamplitude, frequency and phase characteristics of the signals duringrouting and amplification; joining in phase the amplified portions ofthe positive and negative signal at an output stage terminal in a mannerthat results in high beta amplification and of an output signal whencompared to the input signal; and feeding back a portion of the signalin a localized feedback system to increase speed and extend bandwidth.16. A method of amplifying signals in an operational amplifier outputstage, comprising the steps of: generating bias currents in a pre-driversub-stage and a final sub-stage; inputting the signals into thepre-driver sub-stage and a final sub-stage; amplifying the signals intandem in the pre-driver sub-stage and final sub-stage to achieve highbeta amplification of the signal; employing a plurality of translinearloops in the pre-driver sub-stage and final sub-stage such that there isminimal signal loss in the pre-driver sub-stage and the final sub-stage;and using localized feedback principles so as to achieve high speedresponse of the operational amplifier output stage.